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diff --git a/content/projects/archs.md b/content/projects/archs.md new file mode 100644 index 0000000..2d3c0a7 --- /dev/null +++ b/content/projects/archs.md @@ -0,0 +1,350 @@ ++++ +title = "Processors main architecture instruction set" +date = 2026-01-06 ++++ + +--- + +A brief and non-exhaustive compilation of common processors' [ISA](https://en.wikipedia.org/wiki/Instruction_set_architecture); +most of them are [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computer)-based except for the older ones which are more [CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)-based. + +This collection is mostly base on the GNU/Linux architectures' support (see [kernel arch](https://github.com/torvalds/linux/tree/master/arch)), with an additional AVR mention (just not enough juiced for a full OS). + +## TOC + +- [alpha](#alpha-dec-digital-equipment-corporation) +- [arc](#arc-arc-international-argonaut-risc-core) +- [arm and arm64](#arm-and-arm64-arm-advanced-risc-machine-prev-acorn-risc-machine) +- [avr](#avr-atmel) +- [csky](#csky-c-sky) +- [hexagon](#hexagon-qualcomm) +- [loongarch](#loongarch-loongson-technology) +- [m68k](#m68k-motorola) +- [microblaze](#microblaze-xilinx) +- [mips](#mips-mips-technologies-microprocessor-without-interlocked-pipelined-stages) +- [nios2](#nios2-altera) +- [openrisc](#openrisc-open-source) +- [parisc](#parisc-hewlett-packard-hp) +- [powerpc](#powerpc-ibm-international-business-machines) +- [riscv](#riscv-open-source-berkeley) +- [s390](#s390-ibm-international-business-machines) +- [sh](#sh-hitachi) +- [sparc](#sparc-sun-microsystems) +- [x86](#x86-intel-amd) +- [xtensa](#xtensa-espressif-systems) +- [`C` detection function example](#c-detection-function-example) + +## alpha - DEC (Digital Equipment Corporation) + +Initially Alpha AXP - RISC - 64 bit. +[Wiki link.](https://en.wikipedia.org/wiki/DEC_Alpha) + +- EV4: DEC 21064 +- LCA4: DEC 21066 and 21068 +- EV5: DEC 21164 +- PCA5: DEC 21164 +- EV6: DEC 21264 +- EV7: DEC 21364 + +## arc - ARC International (Argonaut RISC Core) + +RISC - 32 and 64 bit. +[Wiki link.](<https://en.wikipedia.org/wiki/ARC_(processor)>) + +## arm and arm64 - ARM (Advanced RISC Machine; prev. Acorn RISC Machine) + +RISC - 32 and 64 bit. +[Wiki link.](https://en.wikipedia.org/wiki/ARM_architecture_family) + +### Naming conventions + +- 64 bit -> aarch64 (ARM arch 64-bit) or arm64; introduced with ARMv8-A +- 32 bit -> arm, aarch32 or armeabi; ARM default architecture +- A specification: Application architecture +- M specification: Microcontroller architecture +- R specification: Real-time architecture + +### Architectures - All RISC + +- ARMv1 - 32 bit: + - ARM1 +- ARMv2 - 32 bit: + - ARM2 and ARM3 + - OpenCores Amber +- ARMv3 - 32 bit: + - ARM6 and ARM7 +- ARMv4 - 32 bit: + - ARM8 + - DEC StrongARM +- ARMv4T - 32 bit: + - ARM7TDMI and ARM9TDMI +- ARMv5TE - 32 bit: + - ARM7EJ, ARM9E and ARM10E + - Intel XScale +- ARMv6 - 32 bit: + - ARM11 +- ARMv6-M - 32 bit: + - ARM Cortex M0, M0+ and M1 +- ARMv7-M - 32 bit: + - ARM Cortex M3 + - Apple M7 +- ARMv7E-M - 32 bit: + - ARM Cortex M4 and M7 +- ARMv8-M - 32 bit: + - ARM Cortex M23 and M33 +- ARMv8.1-M - 32 bit: + - ARM Cortex M55 and M85 +- ARMv7-R - 32 bit: + - ARM Cortex R4, R5, R7 and R8 +- ARMv8-R - 32 and 64 bit: + - ARM Cortex R52 (aarch32) + - ARM Cortex R82 (aarch64) +- ARMv7-A - 32 bit: + - ARM Cortex A5, A7, A8, A9, A12, A15 and A17 + - Qualcomm Scorpion + - Apple Swift (A6) +- ARMv8-A - 32 and 64 bit: + - ARM Cortex A32 (aarch32) + - ARM Cortex A35, A53, A57, A72 and A73 (both aarch32 and aarch64) + - ARM Cortex A34 (aarch64) + - Nvidia Denver (both aarch) + - AMD K12 (both aarch) + - Apple Cyclone A7, Typhoon A8, Twister A9 and Hurricane/Zephyr A10 (both aarch) + - Samsung M1, M2 and M3 (both aarch) +- ARMv8.2-A - 32 and 64 bit: + - ARM Cortex A55, A75, A76, A77, A78 and X1 (both aarch32 and aarch64) + - ARM Cortex A65 (aarch64) + - Nvidia Carmel (both aarch) + - Samsung M4 (both aarch) + - Apple Monsoon/Mistral A11 (aarch64) +- ARMv8.4-A - 64 bit: + - ARM Neoverse V1 + - Apple Lightning/Thunder A13 and FireStorm/Icestrom A14/M1 +- ARMv8.6-A - 64 bit: + - Apple Avalanche/Blizzard A15/M2 and Everest/Sawtooth A16/A17 +- ARMv9.0-A - 64 bit: + - ARM Cortex A510, A710, A715, X2 and X3 + - ARM Neoverse E2, N2 and V2 +- ARMv9.2-A - 64 bit: + - ARM Cortex A520, A720 and X4 + - ARM Neoverse V3 + - Apple A18/M4 + +## avr - Atmel + +RISC - 8 or 32 bit. +[Wiki link.](https://en.wikipedia.org/wiki/AVR_microcontrollers) + +- tinyAVR - 8 bit: + - Atmel ATtiny +- megaAVR - 8 bit: + - Atmel ATmega +- AVR Dx - 8 bit: + - Atmel AVR DA + - Atmel AVR DB + - Atmel AVR DD + - Atmel AVR EA +- XMEGA - 8 bit: + - Atmel ATxmega +- 32 bit AVRs: + - Atmel AVR32 + +## csky - C-SKY + +Chinese CPU ISA designed for embedded Linux with a [Buildroot](https://buildroot.org) support. +[Github link.](https://github.com/c-sky) + +## hexagon - Qualcomm + +Known as QDSP6 (Qualcomm Digital Signal Processing, 6th gen.) - VLIW - 32 and 64 bit. +[Wiki link.](https://en.wikipedia.org/wiki/Qualcomm_Hexagon) + +- QDSP6 V1 +- QDSP6 V2 +- QDSP6 V3, 1st and 2nd gen. +- QDSP6 V4: + - Qualcomm Snapdragon 600 +- QDSP6 V5: + - Qualcomm Snapdragon 410/412/800/801 +- QSP6 V6: + - Qualcomm Snapdragon 820/821/636/660 +- QDSP6 V7: + - Qualcomm Snapdragon 778G/778G+/780G/782G/888/888+ + +## loongarch - Loongson Technology + +RISC - 32 and 64 bit. +[Doc. link.](https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html) + +- LA32 - 32 bit +- LA64 - 64 bit + +## m68k - Motorola + +Known as the Motorola 68000 series, 680x0, m68000 or 68k - CISC - 32 bit. +[Wiki link.](https://en.wikipedia.org/wiki/Motorola_68000_series) + +- Gen. 1 - 16 or 32 bit: + - Motorola 68000 and 68010 +- Gen. 2 - 32 bit: + - Motorola 68010 and 68020 +- Gen. 3 - 32 bit: + - Motorola 68040 +- Gen. 4 - 32 bit: + - Motorola 68060 + +## microblaze - Xilinx + +Designed for the PS part of FPGA chips (AXI support) - RISC - 32 or 64 bit. +[Wiki link.](https://en.wikipedia.org/wiki/MicroBlaze) + +## mips - MIPS Technologies (Microprocessor without Interlocked Pipelined Stages) + +RISC - 32 or 64 bit. + +- MIPS I - 32 bit +- MIPS II - 32 bit +- MIPS III - 64 bit +- MIPS IV - 64 bit +- MIPS V - 64 bit +- MIPS32/MIPS64 - 32 or 64 bit +- microMIPS - 16 or 32 bit + +## nios2 - Altera + +Designed for the PS part of FPGA chips (Avalon support) - RISC - 32 bit. + +- NiosII/f +- NiosII/s +- NiosII/e + +## openrisc - open-source + +Currently one version: OR1k - RISC - 32 or 64 bit. +[Wiki link.](https://en.wikipedia.org/wiki/OpenRISC) + +## parisc - Hewlett-Packard (HP) + +Known as PA-RISC (Precision Architecture RISC), HP/PA or HPPA (Hewlett Packard Precision Architecture) - RISC - 32 or 64 bit. + +- TS, CS and NS series +- PCX series +- Mako +- Shortfin + +## powerpc - IBM (International Business Machines) + +Derived from Power ISA, known as the IBM RS64 family - RISC - 64 bit. + +- RS64 or A35 + - IBM Apache +- RS64-II or A50 + - IBM Northstar +- RS64-III + - IBM Pulsar and later IStar +- RS64-IV + - IBM Sstar + +## riscv - open-source (Berkeley) + +Not yet implemented in real hardware - RISC - 32, 64 or 128 bit. +[Wiki link.](https://en.wikipedia.org/wiki/RISC-V) + +## s390 - IBM (International Business Machines) + +Known as the IBM System/390 family, 5th gen. of the System/360 ISA - CISC - 32 bit. +[Wiki link.](https://en.wikipedia.org/wiki/IBM_System/390) + +## sh - Hitachi + +Known as SuperH or SH - RISC - 32 bit. +[Wiki link.](https://en.wikipedia.org/wiki/SuperH) + +- SH-1 -2 -3 +- SH-4 - co-designed with STMicroelectronics + +## sparc - Sun Microsystems + +SPARC (Scalable Processor ARChitecture) - RISC - 64 bit. +[Wiki link.](https://en.wikipedia.org/wiki/SPARC) + +## x86 - Intel, AMD + +Known as 80x86, 8086, IA (Intel Architecture) or x86abi family. + +- x86-16 - 16 bit CISC: + - Intel 8086 + - Intel 8088 +- IA-32 - 32 bit RISC/APIC -> known as x86, x86_32, win32, ix86 or i386: + - Intel Pentium + - Cyrix Cx5x86 + - Intel Celeron + - AMD K6 +- IA-64 - 64 bit EPIC: + - Intel Itanium +- x86-64 - 64 bit RISC → extension of IA-32; known as x86_64, x64, AMD64 or Intel64; most common arch in modern PCs: + - Intel Atom + - Intel Core series + - Intel Xeon + - AMD Ryzen series + - AMD APU series + - Zhaoxin WuDaoKou + +## xtensa - Espressif Systems + +Known for the ESP32 series (XTensa LX6) - post-RISC - 32 bit. +[Doc. link](https://github.com/espressif/xtensa-isa-doc) + +## `C` detection function example + +```C +/* Get current architecture, detects nearly every architecture. */ +const char *getBuild(void) +{ +#if defined(__x86_64__) || defined(_M_X64) + return "x86_64"; +#elif defined(i386) || defined(__i386__) || defined(__i386) || defined(_M_IX86) + return "x86_32"; +#elif defined(__ARM_ARCH_2__) + return "ARMv2"; +#elif defined(__ARM_ARCH_3__) || defined(__ARM_ARCH_3M__) + return "ARMv3"; +#elif defined(__ARM_ARCH_4T__) || defined(__TARGET_ARM_4T) + return "ARMv4T"; +#elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) + return "ARMv5" +#elif defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6T2__) + return "ARMv6T2"; +#elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) + return "ARMv6"; +#elif defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) + return "ARMv7"; +#elif defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) + return "ARMv7A"; +#elif defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) + return "ARMv7R"; +#elif defined(__ARM_ARCH_7M__) + return "ARMv7M"; +#elif defined(__ARM_ARCH_7S__) + return "ARMv7S"; +#elif defined(__aarch64__) || defined(_M_ARM64) + return "ARM64"; +#elif defined(mips) || defined(__mips__) || defined(__mips) + return "MIPS"; +#elif defined(__sh__) + return "SUPERH"; +#elif defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || defined(__ppc__) || defined(__PPC__) || defined(_ARCH_PPC) + return "POWERPC"; +#elif defined(__PPC64__) || defined(__ppc64__) || defined(_ARCH_PPC64) + return "POWERPC64"; +#elif defined(__sparc__) || defined(__sparc) + return "SPARC"; +#elif defined(__m68k__) + return "M68K"; +#elif defined(__riscv) || defined(__riscv32) || defined(__riscv_) || defined(_riscv) + return "RISCV" +#else + return "UNKNOWN"; +#endif +} +``` |